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Serial peripheral interface (SPI)
Figure 210. Data clock timing diagram
CPOL = 1
CPOL = 0
CPHA =1
RM0008
MISO
(from master)
MSBit
LSBit
8 or 16 bits depending on Data Frame Format (see SPI_CR1)
MOSI
(from slave)
MSBit
LSBit
NSS
(to slave)
Capture strobe
CPHA =0
CPOL = 1
CPOL = 0
MISO
(from master)
MOSI
MSBit
8 or 16 bits depending on Data Frame Format (see SPI_CR1)
MSBit
LSBit
LSBit
(from slave)
NSS
(to slave)
Capture strobe
Note: These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.
1. These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.
Data frame format
Data can be shifted out either MSB-first or LSB-first depending on the value of the
LSBFIRST bit in the SPI_CR1 Register.
Each data frame is 8 or 16 bits long depending on the size of the data programmed using
the DFF bit in the SPI_CR1 register. The selected data frame format is applicable for
transmission and/or reception.
592/995
Doc ID 13902 Rev 9
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